Optimum Structures of a Cascaded Multilevel Inverter for Minimum Number of Power Electronic Devices

In this paper, several optimum structures of a cascaded multilevel inverter is proposed. This optimization is based on generation a constant number of output voltage levels by using minimum number of power switches or dc voltage sources or minimum amount of blocked voltage by power switches. In addition, the optimum structure for a constant number of dc voltage sources by using minimum number of power switches is obtained. In these optimizations, all of the presented algorithms to generate a desired sinosuidal waveform of the cascaded multilevel inverter are considered. Then, the proposed optimum topologies are compared with several conventional cascaded multilevel invereters that have been presented in literature. These comparisons are from the number of required power switches, dc voltag sources, variabilty the magnitude of dc voltage source and the value of blocked voltage by switches points of view. The conduction and switching losses of the proposed topologies are calculated. In addition, a 49-level cascaded inverter based on the proposed optimum topologies is designed. Moreover, the designed topologies are compared to each other from the amount of blocked voltage by swithes, the maximum magnitude of output voltage levels and the number of required power electronic devices such as power switches, driver circuits and diodes points of view. Finally, the ability of the optimium topology in generation all voltage levels (even and odd) by using minimum number of power switches is reconfirmed thruogh PSCAD/EMTDC simulation and experimental results on a 49-level inverter.